Hitachi SH7751 Hardware Manual page 184

(12) Slot FPU Disable Exception


Source: Decoding of an FPU instruction in a delay slot with SR.FD =1


Transition address: VBR + H'0000 0100


Transition operations:
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Slot_fpu_disable_exception()
{
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'00000820;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 145 of 1064