Operand Access Cycle Break - Hitachi SH7751 Hardware Manual

20.3.5

Operand Access Cycle Break

1. In the case of an operand access cycle break, the bits included in address bus comparison vary
as shown below according to the data size specification in the break bus cycle register
(BBRA/BBRB).
Data Size
Quadword (100)
Longword (011)
Word (010)
Byte (001)
Not included in condition (000)
2. When data bus is included in break conditions in channel B
When a data value is included in the break conditions, set the DBEB bit in the break control
register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register
B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt
is generated when all three conditions—address, ASID, and data—are matched. When a
quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32
bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data
units satisfies the data match condition.
Set the IDB1–0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is
specified, the same data should be set in the two bytes comprising bits 15–8 and bits 7–0 in
break data register B (BDRB) and break data mask register B (BDMRB). When word or byte
is set, bits 31–16 of BDRB and BDMRB are ignored.
3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated
by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or
OCBI instruction).
Address Bits Compared
Address bits A31–A3
Address bits A31–A2
Address bits A31–A1
Address bits A31–A0
In quadword access, address bits A31–A3
In longword access, address bits A31–A2
In word access, address bits A31–A1
In byte access, address bits A31–A0
Rev. 3.0, 04/02, page 767 of 1064