Interrupt Exception Handling And Priority - Hitachi SH7751 Hardware Manual

19.2.4

Interrupt Exception Handling and Priority

Table 19.4 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority. Each interrupt source is assigned a unique INTEVT code. The start address of the
interrupt handler is common to each interrupt source. This is why, for instance, the value of
INTEVT is used as an offset at the start of the interrupt handler and branched to in order to
identify the interrupt source.
The order of priority of the on-chip peripheral modules is specified as desired by setting priority
levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD) and interrupt priority
register 00 (INTPRI00). The order of priority of the on-chip peripheral modules is set to 0 by a
reset.
When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default priority order shown in table
19.4.
Updating of interrupt priority registers A to D, and INTPRI00 should only be carried out when the
BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read
one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary
timing internally.
Rev. 3.0, 04/02, page 736 of 1064