Table of Contents
Advertisement
22.1
Overview
The PCI Controller (PCIC) controls the PCI bus and transfers data between memory connected to
the external bus and a PCI device connected to the PCI bus. The ability for PCI devices to be
connected directly not only facilitates the design of systems using PCI buses but also enables
systems to be more compact and capable of high-speed data transfer.
22.1.1
Features
The PCIC has the following features:
Conforms to PCI version 2.1.*
Compatible with PCI bus operating speeds of 33 MHz/66 MHz.
Compatible with 32-bit PCI bus.
Up to four PCI master devices running at 33 MHz or one PCI master device at 66 MHz can be
connected.
Arbitration control is available as a PCI host function.
Can operate as master or target.
When operating as master, PIO and DMA transfer are available.
Four DMA transfer channels.
Six 32-bit x 16 longword internal FIFO (one for target reading, one for target writing, and four
for DMA transfer).
Asynchronous operation of BSC bus clock and PCI bus clock available, and CKIO can be used
as PCI bus clock.
SRAM, DRAM, SDRAM, and MPX*
transfers.
32-bit or 16-bit memory data bus for data transfers with PCI bus (32-bit bus when connected to
SDRAM).
Support for big endian and little endian local bus (PCI bus operates with little endian, while
internal bus for peripheral modules operates with big endian).
Notes: *1 The PCIC of the SH7751 series does not completely conform to version 2.1 of the PCI
specifications. When configuring a PCI system in which an SH7751-series device is
used, take the necessary steps and confirm the system's operation before using it.
(1) In version 2.1 of the PCI specifications, the I/O space for PCI devices is defined as
being no more than 256 bytes, but the SH7751's specifications require 1 Mbytes of
I/O space for the PCI.
Section 22 PCI Controller (PCIC)
1
2
can be used as external memory for PCI bus data
Rev. 3.0, 04/02, page 801 of 1064
Advertisement
Table of Contents
