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22.2.37 PCI Clock Control Register (PCICLKR)
Bit:
31
—
Initial value:
0
PCI-R/W:
—
PP Bus-R/W:
R
Bit:
7
—
Initial value:
0
PCI-R/W:
—
PP Bus-R/W:
R
The PCI clock control register (PCICLKR) controls the stopping of the local bus clock (BCLK) in
the PCIC and the PCI bus clock. This 32-bit read/write register can be accessed from the PP bus.
The PCICLKR register is initialized to H'00000000 at a power-on reset. It is not initialized at a
software reset.
When the PCI bus clock is input from the external input pin
stopped by setting the PCICLKSTOP bit to 1. Likewise, the local bus clock can be stopped by
setting the BCLKSTOP bit to 1.
When the PCI bus clock is input via the CKIO pin, setting BCLKSTOP to 1 stops both the B
the PCIC and the feedback input clock from CKIO.
Writing to this register is valid only when bits 31 to 24 are H'A5.
Bits 31 to 2—Reserved: These bits are always read as 0. When writing, always write H'A5 to bits
31 to 24, and 0 to the other bits. Always write 0 to these bits when writing.
Bit 1—PCICLK Stop Control (PCICLKSTOP): Controls the stopping of the clock input via the
PCICLK pin.
Bit 1: PCICLKSTOP
0
1
Rev. 3.0, 04/02, page 872 of 1064
30
29
—
—
0
0
—
—
R
R
6
5
—
—
0
0
—
—
R
R
Description
PCICLK input enabled
Stop PCICLK input
. . .
11
. . .
—
. . .
0
. . .
—
. . .
R
4
3
—
—
0
0
—
—
R
R
, the PCI bus clock can be
10
9
—
—
0
0
—
—
R
R
2
1
—
PCICLKS
BCLKST
TOP
OP
0
0
—
—
R
R/W
R/W
(Initial value)
8
—
0
—
R
0
0
—
in
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