Figure 13.50 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface - Hitachi SH7751 Hardware Manual

Tpci2 Tpci2w
Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w
CKIO
A25–A1
A0
RD/
( )
(read)
D15–D0
(read)
( )
(write)
D15–D0
(write)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface

Rev. 3.0, 04/02, page 432 of 1064