Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment
Operation
Access
Size
Address No.
Byte
4n
1
4n+1
1
4n+2
1
4n+3
1
Word
4n
1
4n+2
1
Long-
4n
1
word
Quad-
8n
1
word
8n+4
2
Data Bus
D31–D24
D23–D16
—
—
—
—
Data
7–0
Data
—
7–0
—
—
Data
Data
15–8
7–0
Data
Data
31–24
23–16
Data
Data
31–24
23–16
Data
Data
63–56
55–48
D15–D8
D7–D0
DQM3
—
Data
7–0
Data
—
7–0
—
—
—
—
Asserted
Data
Data
15–8
7–0
—
—
Asserted Asserted
Data
Data
Asserted Asserted Asserted Asserted
15–8
7–0
Data
Data
Asserted Asserted Asserted Asserted
15–8
7–0
Data
Data
Asserted Asserted Asserted Asserted
47–40
39–32
Rev. 3.0, 04/02, page 363 of 1064
Strobe Signals
,
,
,
,
,
,
DQM2
DQM1
Asserted
Asserted
Asserted Asserted
,
,
DQM0
Asserted