Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus  External Device Data Transfer; Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword - Hitachi SH7751 Hardware Manual

CKIO
DBREQ
BAVL
TR
A25–A0
D31–D0
CMD
TDACK
ID1, ID0
Start of data transfer
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/
CKIO
DBREQ
BAVL
TR
A25–A0
D31–D0
DTR
CMD
DQMn
TDACK
ID1, ID0

Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,

Quadword/External Bus
Wait for next DMA request
CA
DTR
RD
 
External Bus External Device Data Transfer
CA
D0
RD
 
CA
D0 D1 D2 D3
RD
CA
D2
Idle cycle
RD
External Device Data Transfer
Rev. 3.0, 04/02, page 539 of 1064
D0 D1 D2 D3
CA
D3
Idle cycle
Idle cycle
RD