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Bit 15: TRWL2
Bit 14: TRWL1
0
0
1
1
0
1
Note: * Inhibited in RAS down mode
Bits 12 to 10—CAS-Before-RAS Refresh
DRAM interface is set, these bits set the
When the synchronous DRAM interface is set, the bank active command is not issued for a period
of TRC* + TRAS after an auto-refresh command is issued.
Bit 12: TRAS2
Bit 11: TRAS1
0
0
1
1
0
1
Note: * Bits 29 to 27: RAS precharge interval at end of refresh
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
Bit 13: TRWL0
0
1
0
1
0
1
0
1
Assertion Period (TRAS2–TRAS0): When the
assertion period in CAS-before-RAS refreshing.
Bit 10: TRAS0
Assertion Time
0
2
1
3
0
4
1
5
0
6
1
7
0
8
1
9
Write Precharge ACT Delay Time
1 (Initial value)
2
3*
4*
5*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Command
Interval after
/DRAM
Synchronous
DRAM Refresh
4 + TRC*
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
Rev. 3.0, 04/02, page 347 of 1064
(Initial value)
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