Pci Dma Transfer Counter Register [3:0] (Pcidtc [3:0]) - Hitachi SH7751 Hardware Manual

The transfer address of a byte boundary or character boundary can be set, but the 2 least
significant bits of the register are ignored, and the data of the longword boundary is transferred.
Note that the local bus starting address set in this register is the external address of the SH.
Always write to this register prior to starting DMA transfers. After a DMA transfer starts, the
register value is not retained. Always re-set this register before starting a new DMA transfer after
a DMA transfer has completed.
Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bits 28 to 0—DMA Transfer Local Bus Starting Address (PDLA28 to 0): These bits set the
starting address of the local bus (external address of SH) for DMA transfer. Bits 28 to 26 indicate
the local bus area.

22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0])

Bit: 31
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
PTC23
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
Bit: 15
PTC15
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
Bit: 7
PTC7
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
Rev. 3.0, 04/02, page 860 of 1064
30 29
— —
0 0
R R
R R
22 21
PTC22 PTC21 PTC20
0 0
R/W R/W
R/W R/W
14 13
PTC14 PTC13 PTC12
0 0
R/W R/W
R/W R/W
6 5
PTC6 PTC5
0 0
R/W R/W
R/W R/W
28 27
— —
0 0
R R
R R
20 19
PTC19 PTC18
0 0
R/W R/W
R/W R/W
12 11
PTC11 PTC10
0 0
R/W R/W
R/W R/W
4 3
PTC4 PTC3
0 0
R/W R/W
R/W R/W
26 25
— PTC25 PTC24
0 0
R R/W
R R/W
18 17
PTC17 PTC16
0 0
R/W R/W
R/W R/W
10 9
PTC9 PTC8
0 0
R/W R/W
R/W R/W
2 1
PTC2 PTC1 PTC0
0 0
R/W R/W
R/W R/W
24
0
R/W
R/W
16
0
R/W
R/W
8
0
R/W
R/W
0
0
R/W
R/W