Hitachi SH7751 Hardware Manual page 681

Bit 6: RIE
0
1
Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then
clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be
cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by
clearing the RIE and REIE bits to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE
0
1
Note: * Serial transmission is started when transmit data is written to SCFTDR2 in this state.
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set
to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE
0
1
Notes: *1 Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER
flags, which retain their states.
*2 Serial transmission is started when a start bit is detected in this state.
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
made, the reception format decided, and the receive FIFO reset, before the RE bit is set
to 1.
Rev. 3.0, 04/02, page 642 of 1064
Description
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request disabled*
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request enabled
Description
Transmission disabled
Transmission enabled*
Description
1
Reception disabled*
2
Reception enabled*
(Initial value)
(Initial value)
(Initial value)