Table 23.22 Clock And Control Signal Timing - Hitachi SH7751 Hardware Manual

Superh risc engine
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Table 23.22 Clock and Control Signal Timing

(HD6417751BP167, HD6417751F167, HD6417751BP167I, HD6417751F167I)
HD6417751BP167, HD6417751F167: V
C
= 30 pF
L
HD6417751BP167I, HD6417751F167I: V
C
= 30 pF
L
Item
EXTAL
PLL1/PLL2
clock input
operating
frequency
PLL1/PLL2
not operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock
PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode settling t
MD reset setup time
MD reset hold time

assert time
PLL synchronization settling time
Standby return oscillation settling time 1
Standby return oscillation settling time 2
Standby return oscillation settling time 3
IRL interrupt determination time
(RTC used, standby mode)

reset hold time
Notes:
1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 28 MHz.
When a 3rd overtone crystal resonator is used, an external tank circuit is necessary.
2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected
to the CKIO pin should be a maximum of 50 pF.
Rev. 3.0, 04/02, page 954 of 1064
= 3.0 to 3.6 V, V
DDQ
= 3.0 to 3.6 V, V
DDQ
Symbol
1/2 divider
f
EX
operating
1/2 divider not
f
EX
operating
1/2 divider
f
EX
operating
1/2 divider not
f
EX
operating
t
EXcyc
t
EXL
t
EXH
t
EXr
t
EXf
f
OP
f
OP
t
cyc
t
CKOL1
t
CKOH1
t
CKOr
t
CKOf
t
CKOL2
t
CKOH2
t
OSC1
OSCMD
t
MDRS
t
MDRH
t
RESW
t
PLL
t
OSC2
t
OSC3
t
OSC4
t
IRLSTB
t
TRSTRH
= 1.8 V, Ta = –20 to 75
DD
= 1.8 V, Ta = –40 to 85
DD
Min
Max
Unit
30
56
MHz
15
28
2
56
1
28
17.8
1000
ns
3.5
ns
3.5
ns
4
ns
4
ns
30
84
MHz
1
84
MHz
11.9
1000
ns
1
ns
1
ns
3
ns
3
ns
3
ns
3
ns
10
ms
10
ms
3
t
cyc
20
ns
20
t
cyc

200
s
10
ms
5
ms
5
ms

200
s
0
ns

C,

C,
Figure
23.1
23.1
23.1
23.1
23.1
23.2(1)
23.2(1)
23.2(1)
23.2(1)
23.2(1)
23.2(2)
23.2(2)
23.3, 23.5
23.3, 23.5
23.3, 23.5
23.3, 23.4, 23.5,
23.6
23.9, 23.10
23.4, 23.6
23.7
23.8
23.10
23.3, 23.5

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