Hitachi SH7751 Hardware Manual page 515




Bit 19— Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR3.
Bit 19: DS
0
1
Notes: Level detection burst mode when TM = 1 and DS = 0
Edge detection burst mode when TM = 1 and DS = 1
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 18: RL
0
1
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR1–CHCR3. (DDT mode: TDACK)
Bit 17: AM
0
1
Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 16: AL
0
1
Rev. 3.0, 04/02, page 476 of 1064


pin used in external request mode.
Description
Low level detection
Falling edge detection


) is an active-high or active-low output.
Description
DRAK is an active-high output
DRAK is an active-low output
Description
DACK is output in read cycle
DACK is output in write cycle
Description
Active-high output
Active-low output
(Initial value)
(Initial value)
(Initial value)
(Initial value)