Figure 14.9 Example Of Dma Transfer In Cycle Steal Mode; Figure 14.10 Example Of Dma Transfer In Burst Mode - Hitachi SH7751 Hardware Manual

Bus cycle
CPU

Figure 14.9 Example of DMA Transfer in Cycle Steal Mode

Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. Bus release by means of
refresh requests conform to the DMAC burst mode transfer priority specification in bus control
register 1 (BCRL.DMABST). With


when is driven high the bus passes to another bus master after the end of the DMAC
transfer request that has already been accepted, even if the transfer end condition has not been
satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and
1).
Bus cycle
CPU

Figure 14.10 Example of DMA Transfer in Burst Mode

Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode
setting can also be made.
Rev. 3.0, 04/02, page 498 of 1064
CPU CPU DMAC
Read




CPU CPU DMAC
Bus returned to CPU
DMAC CPU
Write
low level detection in external request mode, however,
level detection (CHCRn.DS = 0, CHCRn.TM =
DMAC DMAC
DMAC DMAC CPU
Read Write
DMAC DMAC DMAC
CPU

and
CPU