Figure 4.6 Configuration Of Instruction Cache (Sh7751) - Hitachi SH7751 Hardware Manual

Figure 4.6 shows the configuration of the instruction cache in the SH7751.
Figure 4.7 shows the configuration of the instruction cache in the SH7751R.
Effective address
31 26 25
IIX
22
MMU
19

Figure 4.6 Configuration of Instruction Cache (SH7751)

Rev. 3.0, 04/02, page 100 of 1064
[12]
8
Address array
Tag V
0
255 19 bits 1 bit
Compare
Hit signal
13 12 11 10 9
[11:5]
Longword (LW) selection
3
LW0 LW1 LW2 LW3
32 bits 32 bits 32 bits 32 bits
5 4 3 2 1 0
Data array
LW4 LW5 LW6 LW7
32 bits 32 bits 32 bits 32 bits
Read data