Figure 23.15 Sram Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) - Hitachi SH7751 Hardware Manual

Superh risc engine
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CKIO
A25–A0
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)

Rev. 3.0, 04/02, page 970 of 1064
T1
Tw
Twe
t
AD
t
CSD
t
RWD
t
t
RSD
RSD
t
WED1
t
WEDF
t
t
WDD
WDD
t
t
BSD
BSD
t
RDYS
t
RDYS
t
DACD
t
DACD
t
DACDF
t
DACD
T2
t
AD
t
CSD
t
RWD
t
RSD
t
t
RDS
RDH
t
WEDF
t
WDD
t
RDYH
t
RDYH
t
DACD
t
DACDF
t
DACD

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