Figure 13.38(1) Synchronous Dram Mode Write Timing (Pall) - Hitachi SH7751 Hardware Manual

Synchronous DRAM mode register setting should be executed once only after power-on reset and
before synchronous DRAM access, and no subsequent changes should be made.
CKIO
Bank
Precharge-sel
Address
RD/
D31–D0
CKE

Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL)

TRp1 TRp2 TRp3
(High)
TRp4 TMw1 TMw2
Rev. 3.0, 04/02, page 415 of 1064
TMw3 TMw4 TMw5