Figure 13.6 Basic Timing Of Sram Interface - Hitachi SH7751 Hardware Manual

CKIO
A25–A0
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
SA: Single address DMA
DA: Dual address DMA

Figure 13.6 Basic Timing of SRAM Interface

T1 T2
Rev. 3.0, 04/02, page 371 of 1064