22.2.38 Pcic-Bsc Registers - Hitachi SH7751 Hardware Manual

Bit 0—BCLK Stop Control (BCLKSTOP): Controls the stopping of the B
CKIO input clock in the PCIC.
Bit 0: BCLKSTOP
0
1

22.2.38 PCIC-BSC Registers

PCIC Bus Control Register 1 (PCIBCR1)
PCIC Bus Control Register 2 (PCIBCR2)
PCIC Bus Control Register 3 (PCIBCR3)*
PCIC Wait Control Register 1 (PCIWCR1)
PCIC Wait Control Register 2 (PCIWCR2)
PCIC Wait Control register 3 (PCIWCR3)
PCIC Discrete Memory Control Register (PCIMCR)
Because PCI bus data is stored, in the PCIC, in memory on the local bus, the PCIC is equipped
with an internal bus controller (PCIC-BSC). The PCIC-BSC performs the same type of control as
the slave function of the bus controller (BSC). There are six registers in the PCIC-BSC: PCIBCR1
(equivalent to the BCR1 of the BSC), PCIBCR2 (equivalent to the BCR2 of the BSC), PCIBCR3
(equivalent to the BCR3 of the BSC), PCIWCR1 (equivalent to the WCR1 of the BSC),
PCIWCR2 (equivalent to the WCR2 of the BSC), PCIWCR3 (equivalent to the WCR3 of the
BSC), and PCIMCR (equivalent to the MCR of the BSC). Each is a 32-bit register. BCR2 and
BCR3 are 16-bit registers, but PCIBCR2 and PCIBCR3 should be accessed by longword access.
The low 16 bits of PCIBCR2 and PCIBCR3 corresponds to the 16 bits of these registers,
respectively. See section 13, Bus State Controller (BSC), for details of the initial values, etc.


The PCIC-BSC performs the same operations as the slave mode of the BSC. Therefore, the
MATER bit of the PCI bus control register 1 (PCIBCR1) shows the slave status.


Because the PCIC-BSC operates in slave mode, the bus privilege is handed to the BSC once
per bus cycle.
Note, however, that the external memory capable of data transfers to the PCI bus is SRAM,
DRAM, synchronous DRAM, and MPX*
(only 32-bit in the case of synchronous DRAM).
Do not specify other external memory types (burst ROM, MPX, byte control SRAM or PCMCIA)
as the external memory for data transfers with the PCI bus.


Because the PCIC-BSC operates in slave mode, the RAS-down mode of DRAM and SDRAM
is not available.


The local bus supports both big and little endian. However, the PCI bus supports only little
endian.
Description
B
input enabled
Stop B
input
1
2
. Also, the memory data width is 32-bit or 16-bit only

input clock and
(Initial value)
Rev. 3.0, 04/02, page 873 of 1064