Figure 23.16 Sram Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1) - Hitachi SH7751 Hardware Manual

CKIO
–
A25 A0
RD/
–
D31 D0
(read)
–
D31 D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
TS1 T1
t
AD
t
CSD
t
RWD
t
RSD
t
WED1
t
WEDF
t t
WDD WDD
t t
BSD BSD
t t
DACD DACD
t
DACDF
t
DACD
Insertion, AnS = 1, AnH = 1)
T2 TH1
t
AD
t
CSD
t
RWD
t t
RSD RSD
t t
RDS RDH
t
WEDF
t
WDD
t
DACD
t
DACDF
t
DACD
Rev. 3.0, 04/02, page 971 of 1064