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22.2.6
PCI Configuration Register 5 (PCICONF5)
Bit:
31
BASE031 BASE030 BASE029 BASE028 BASE027 BASE026 BASE025 BASE024
Initial value:
0
PCI-R/W:
R/W
PP Bus-R/W:
R/W
Bit:
23
BASE023 BASE022 BASE021 BASE020 BASE019 BASE018 BASE017 BASE016
Initial value:
0
PCI-R/W:
R/W
PP Bus-R/W:
R/W
Bit:
15
BASE015 BASE014 BASE013 BASE012 BASE011 BASE010 BASE09 BASE08
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
Bit:
7
BASE07 BASE06 BASE05 BASE04 LA0PREF
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
The PCI configuration register 5 (PCICONF5) is a 32-bit read/partial-write register that
accommodates the memory space base address PCI configuration register stipulated in the PCI
local bus specifications. This register holds the high bits (12 max. in bits 31 to 20) of the address
used when a device on the PCI bus accesses local memory on the SH local bus using memory
transfer commands. Allocate at least the capacity set in the local space register 0 (PCILSR0) as
PCI bus memory space.
Bits 19 to 0 are fixed in hardware. Of writable bits 31 to 20, those that hold valid values differ
according to the value set in PCILSR0.
30
29
0
0
R/W
R/W
R/W
R/W
R/W
R/W
22
21
0
0
R/W
R/W
R/W
R/W
R/W
R/W
14
13
0
0
R
R
R
R
6
5
0
0
R
R
R
R
28
27
0
0
R/W
R/W
R/W
R/W
20
19
0
0
R
R
12
11
0
0
R
R
R
R
4
3
LA0TYPE1 LA0TYPE0
0
0
R
R
R
R
Rev. 3.0, 04/02, page 823 of 1064
26
25
24
0
0
R/W
R/W
R/W
R/W
18
17
16
0
0
R
R
R
R
10
9
0
0
R
R
R
R
2
1
LA0ASI
0
0
R
R
R
R
0
0
R
R
8
0
R
R
0
0
R
R
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