Table 21.3 Structure of Boundary Scan Register (cont)
No.
Pin name
29
D4
28
D3
27
D3
26
D3
25
D2
24
D2
23
D2
22
D1
21
D1
20
D1
19
D0
18
D0
17
D0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
to TDO
Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set
LOW.
/
/
Type
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
Rev. 3.0, 04/02, page 797 of 1064