Hitachi SH7751 Hardware Manual page 853

Bit 27: STA
0
1


Bits 26 and 25—
response timing when the PCIC is operating as a target.
Bit 26: DEV1
0
1
Bit 24—Data Parity Status (DPD): Indicates the

when the PCIC is operating as the master. This bit is set only when the parity error response
bit (bit 6) is 1.
Bit 24: DPD
0
1
Bit 23—High-Speed Back-To-Back Status (FBBC): Shows whether a high-speed back-to-back
transfer to a different target can be accepted when the PCIC is operating as a target.
Bit 23: FBBC
0
1
Bit 22—User Defined Function System (UDF): Shows whether user defined functions are
supported.
Bit 22: UDF
0
1
Bit 21—66 MHz Operating Status (66M): Shows whether 66 MHz operation is supported.
Rev. 3.0, 04/02, page 814 of 1064
Description
No transaction termination using target abort by target device (Initial value)
Transaction termination by target abort by target device. Notification by
target device
Timing Status (DEV1 and 0): These bits indicate the
Bit 25: DEV0
0
1
0
1
Description
Data parity not detected
Data parity occurred
Description
The target does not have a high-speed back-to-back transaction function for
use with other targets
The target has a high-speed back-to-back transaction function for use with
other targets
Description
This device does not support user functions
This device supports user functions
Description
High-speed (not supported)
Medium speed
Low speed (not supported)
Reserved

assert operation or the detection of

(Initial value)
(Initial value)
(Initial value)
(Initial value)