Figure 19.1 Block Diagram Of Intc - Hitachi SH7751 Hardware Manual

Superh risc engine
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NMI
IRL3–
IRL0
4
(Interrupt request)
TMU
(Interrupt request)
RTC
(Interrupt request)
SCI
(Interrupt request)
SCIF
(Interrupt request)
WDT
(Interrupt request)
REF
(Interrupt request)
DMAC
(Interrupt request)
H-UDI
(Interrupt request)
GPIO
(Interrupt request)
PCIC
TMU:
Timer unit
RTC:
Realtime clock unit
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
WDT:
Watchdog timer
REF:
Memory refresh controller section of the bus state controller
DMAC:
Direct memory access controller
H-UDI:
Hitachi user debug interface unit
GPIO:
I/O port
PCIC:
PCI bus controller
ICR:
Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D
INTPRI00:
Interrupt priority register 00
SR:
Status register
Rev. 3.0, 04/02, page 730 of 1064
Input control
4
ICR

Figure 19.1 Block Diagram of INTC

Com-
Priority
parator
identifier
IPR
IPRA–IPRD,
INTPRI00
Bus interface
Interrupt
request
SR
I3 I2 I1 I0
CPU
INTC

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