Hitachi SH7751 Hardware Manual page 880

Bit 5—Mode 10 Pin Monitor (MD10): Monitors the
reset by means of the
Bit 5: MD10
0
1
Bit 4—Mode 9 Pin Monitor (MD9): Monitors the

by means of the
Bit 4: MD9
0
1
     
Bit 3— Output (SERR): Software control of
8 (SER) of the PCICONFI register is "1". When "1" is written to this bit,
clock. This bit always returns "0" when read. Used when the PCIC is not the host. If used when
the PCIC is the host, an
Bit 3: SERR
0
1
 
 
Bit 2— Output (INTA): Software control of
Bit 2: INTA
0
1
Bit 1—PCIRST Output Control (RSTCTL): Controls the
on reset before output. This field is reset only at a power-on reset. Do not use the field when the
PCIC is non-host.
Bit 1: PCIRST
0
1

pin.
Description
Host bridge function (arbitration) enabled
Host bridge function disabled
pin.
Description
PCICLK used as PCI clock
Feedback input clock from CKIO used as PCI clock

assert interrupt is generated for the SH7751 Series.
Description



pin at Hi-Z



Assert (Low output)
Description

pin at Hi-Z (driven to High by pull-up resistor)

Assert (Low output)
Description


Negate (High output)


Assert (Low output)
 
/MD10 pin value in a power-on
 
/MD9 pin value in a power-on reset

output. This bit is valid only when bit
 
(valid only when PCIC is not host)
 
output. ORed with a power-
Rev. 3.0, 04/02, page 841 of 1064

is asserted for 1
(Initial value)
(Initial value)
(Initial value)