Figure 23.18 Burst Rom Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait) - Hitachi SH7751 Hardware Manual

Superh risc engine
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Figure 23.18 Burst ROM Bus Cycle
(1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait)
Rev. 3.0, 04/02, page 973 of 1064

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