Hitachi SH7751 Hardware Manual page 514

Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits
specify the space attribute for PCMCIA interface area access.
Bit 27: DSA2 Bit 26: DSA1
0 0
1
1 0
1
Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA interface area access. This bit selects the wait control register in the
BSC that performs area 5 and 6 wait cycle control.
Bit 24: DTC
0
1
Note: For details, see section 13.3.7, PCMCIA Interface.
Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 25: DSA0
0
1
0
1
0
1
0
1
Description
CS5 space wait cycle selection
Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits
A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the
PCMCIA control register (PCR), are selected
CS6 space wait cycle selection
Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits
A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the
PCMCIA control register (PCR), are selected
Description
Reserved in PCMCIA access
Dynamic bus sizing I/O space
8-bit I/O space
16-bit I/O space
8-bit common memory space
16-bit common memory space
8-bit attribute memory space
16-bit attribute memory space
Rev. 3.0, 04/02, page 475 of 1064
(Initial value)
(Initial value)