Figure 5.3 Example Of General Exception Acceptance Order - Hitachi SH7751 Hardware Manual

Pipeline flow:
Instruction n
Instruction n+1
Instruction n+2
Instruction n+3
Order of detection:
General illegal instruction exception (instruction n+1) and
TLB miss (instruction n+2) are detected simultaneously
TLB miss (instruction n)
Order of exception handling:
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n+1)
Re-execution of instruction n+1
TLB miss (instruction n+2)
Re-execution of instruction n+2
Execution of instruction n+3

Figure 5.3 Example of General Exception Acceptance Order

TLB miss (data access)
IF ID EX MA
IF ID EX MA
General illegal instruction exception
TLB miss (instruction access)
IF ID EX
IF ID
Program order
WB
WB
MA WB
IF:
ID: Instruction decode
EX: Instruction execution
EX MA WB
MA: Memory access
WB: Write-back
1
2
3
4
Rev. 3.0, 04/02, page 127 of 1064
Instruction fetch