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The read/write strobe signal address and
setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3
register.
When a PCMCIA interface is used, the address
and
setup and hold times with respect
to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and
AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait
cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in
PCR is added to the number of waits set in WCR2.
13.3.3
SRAM Interface
Basic Timing: The SRAM interface of the SH7751 Series uses strobe signal output in
consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the SRAM
timing of normal space accesses. A no-wait normal access is completed in two cycles. The
signal is asserted for one cycle to indicate the start of a bus cycle. The
signal is asserted on
the T1 rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation
period in case of access at minimum pitch.
There is no access size specification when reading. The correct access address is output to the
address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in
the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the
signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and
Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this transfer.
Rev. 3.0, 04/02, page 370 of 1064
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