Figure 23.32 Synchronous Dram Bus Cycle: Auto-Refresh (Tras = 1, Trc [2:0] = 001) - Hitachi SH7751 Hardware Manual

TRr1
CKIO
t
AD
Bank
Precharge-sel
Address
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D31–D0
(write)
CKE
t
DACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001)

TRr2 TRr3 TRr4
t t
CSD CSD
t t
RASD RASD
t t
CASD2 CASD2
TRrw TRr5 Trc
t
RWD
t
CASD2
t
BSD
Rev. 3.0, 04/02, page 987 of 1064
Trc Trc
t
AD
t
CSD
t
RASD
t
DQMD
t
WDD
t
DACD