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Bit 0—PCIC Internal Register Initialization Control Bit (CFINIT): After the SH initializes
the PCI registers, setting this bit enables access from the PCI bus. During initialization, no bus
privileges are granted to other devices on the PCI bus while operating as the host. When operating
not as the host, a retry is returned without the access from the PCI bus being accepted.
Bit 0: CFINIT
0
1
22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])
Bit:
31
—
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
Bit:
23
PLSR23 PLSR22 PLSR21 PLSR20
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R/W
Bit:
15
—
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
Bit:
7
—
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
The PCI local space register [1:0] (PCILSR [1:0]) specifies the capacities of the two local address
spaces (address space 0 and address space 1) supported when a device on the PCI bus performs a
Rev. 3.0, 04/02, page 842 of 1064
Description
Initialization busy
Initialization complete
30
29
—
—
0
0
R
R
R
R
22
21
0
0
R
R
R/W
R/W
14
13
—
—
0
0
R
R
R
R
6
5
—
—
0
0
R
R
R
R
28
27
PLSR28 PLSR27 PLSR26 PLSR25 PLSR24
0
0
R
R
R/W
R/W
20
19
—
0
0
R
R
R/W
R
12
11
—
—
0
0
R
R
R
R
4
3
—
—
0
0
R
R
R
R
(Initial value)
26
25
0
0
R
R
R/W
R/W
R/W
18
17
—
—
0
0
R
R
R
R
10
9
—
—
0
0
R
R
R
R
2
1
—
—
0
0
R
R
R
R
24
0
R
16
—
0
R
R
8
—
0
R
R
0
—
0
R
R
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