Figure 23.33 Synchronous Dram Bus Cycle: Self-Refresh (Trc [2:0] = 001) - Hitachi SH7751 Hardware Manual

TRs1
CKIO
t
AD
Bank
Precharge-sel
Address
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D31–D0
(write)
CKE
t
DACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001)

Rev. 3.0, 04/02, page 988 of 1064
TRs2 TRs3 TRs4
t
CSD
t
CSD
t
RASD
t
RASD
t
CASD2
t
CASD2
t
CKED
Trc
TRs5 Trc
t
RWD
t
CASD2
t
WDD
t
BSD
t
CKED
Trc
t
AD
t
CSD
t
RASD
t
DQMD
t
DACD