Hitachi SH7751 Hardware Manual page 441

RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses
to the same row address. When the RASD bit in MCR is 1, read/write command accesses are
performed using commands without auto-precharge (READ, WRIT). In this case, precharging is
not performed when the access ends. When accessing the same row address in the same bank, it is
possible to issue the READ or WRIT command immediately, without issuing an ACTV command,
in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided
into two or four banks, it is possible to activate one row address in each bank. If the next access is
to a different row address, a PRE command is first issued to precharge the relevant bank, then
when precharging is completed, the access is performed by issuing an ACTV command followed
by a READ or WRIT command. If this is followed by an access to a different row address, the
access time will be longer because of the precharging performed after the access request is issued.
In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl +
Tpc cycles after issuance of the WRITA command. When RAS down mode is used, READ or
WRIT commands can be issued successively if the row address is the same. The number of cycles
can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance
of the PRE command and the ACTV command is determined by bits TPC2–TPC0 in MCR.
There is a limit on t , the time for placing each bank in the active state. If there is no guarantee
RAS
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of t . In this way, it is possible to observe the
RAS
restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures
must be taken in the program to ensure that the banks do not remain active for longer than the
prescribed time.
A burst read cycle without auto-precharge is shown in figure 13.28, a burst read cycle for the same
row address in figure 13.29, and a burst read cycle for different row addresses in figure 13.30.
Similarly, a burst write cycle without auto-precharge is shown in figure 13.31, a burst write cycle
for the same row address in figure 13.32, and a burst write cycle for different row addresses in
figure 13.33.
When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs
the byte specification. As a result, when the READ command is issued in figure 13.28, if the Tc
cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be
carried out. Therefore, the CAS latency should not be set to 1.
When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as
long as accesses to the same row address continue, the operation starts with the cycle in figure
13.28 or 13.31, followed by repetition of the cycle in figure 13.29 or 13.32. An access to a
different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 13.30 or 13.33 is executed instead of
that in figure 13.29 or 13.32. In RAS down mode, too, a PALL command is issued before a refresh
cycle or before bus release due to bus arbitration.
Rev. 3.0, 04/02, page 402 of 1064