Table 7.12 Floating-Point Graphics Acceleration Instructions - Hitachi SH7751 Hardware Manual

Table 7.12 Floating-Point Graphics Acceleration Instructions

Instruction
FMOV DRm,XDn
FMOV XDm,DRn
FMOV XDm,XDn
FMOV @Rm,XDn
FMOV @Rm+,XDn
FMOV @(R0,Rm),XDn
FMOV XDm,@Rn
FMOV XDm,@-Rn
FMOV XDm,@(R0,Rn)
FIPR FVm,FVn
FTRV XMTRX,FVn
FRCHG
FSCHG
Operation

DRm XDn

XDm DRn

XDm XDn

(Rm) XDn
 
(Rm) XDn, Rm + 8

(R0 + Rm) XDn

XDm (Rn)
 
Rn – 8 Rn, XDm (Rn)

XDm (R0+Rn)
inner_product [FVm, FVn]
FR[n+3]
transform_vector [XMTRX, FVn]

FVn

~FPSCR.FR SPFCR.FR

~FPSCR.SZ SPFCR.SZ
Instruction Code
1111nnn1mmm01100 —
1111nnn0mmm11100 —
1111nnn1mmm11100 —
1111nnn1mmmm1000 —
Rm 1111nnn1mmmm1001 —
1111nnn1mmmm0110 —
1111nnnnmmm11010 —
1111nnnnmmm11011 —
1111nnnnmmm10111 —

1111nnmm11101101 —
1111nn0111111101 —
1111101111111101 —
1111001111111101 —
Rev. 3.0, 04/02, page 185 of 1064
Privileged T Bit
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