Hitachi SH7751 Hardware Manual page 855

Bit 6: PER
0
1
Bit 5—VGA Pallet Snoop Control (VPS)
Bit 5: VPS
0
1
Bit 4—Memory Write and Invalidate Control (MWIE): Controls the issuance of memory and
invalidate command when the PCIC is operating as the master.
Bit 4: MWIE
0
1
Bit 3—Special Cycle Control (SPC): Shows whether special cycles are supported when the
PCIC is operating as a target.
Bit 3: SPC
0
1
Bit 2—PCI Bus Master Control (BUM): Controls the bus master operation.
Bit 2: BUM
0
1
Bit 1—Memory Space Control (MES): Controls the access to the memory space when the PCIC
is operating as a target. When this bit is 0, all memory transfers to the PCIC are terminated by
master abort.
Bit 1: MES
0
1
Rev. 3.0, 04/02, page 816 of 1064
Description
Ignore detected parity errors
Respond to detected parity error
Description
VGA-compatible device
The device does not respond to pallet register writes (not supported)
Description
The device uses memory write
The device can execute memory write and invalidate commands (not
supported)
Description
Ignore special cycle
Monitor special cycle (not supported)
Description
Disable bus master operation
Enable bus master operation
Description
Disable access to memory space
Enable access to memory space
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)