Hitachi SH7751 Hardware Manual page 1057

Module Item


DMAC setup
time


hold time
DRAKn delay time t
INTC NMI pulse width
(high)
NMI pulse width
(low)
H-UDI Input clock cycle
Input clock pulse
width (high)
Input clock pulse
width (low)
Input clock rise
time
Input clock fall time t


setup
time


hold time t
TDI/TMS setup
time
TDI/TMS hold time t
TDO delay time
ASE-PINBRK pulse
width
Notes: *1 Pcyc: P clock cycles
*2 V = 3.0 to 3.6 V, V
DDQ
*3 V = 3.0 to 3.6 V, V
DDQ
(HD6417751BP167, HD6417751F167)
V = 3.0 to 3.6 V, V
DDQ
(HD6417751BP167I, HD6417751F167I)
Rev. 3.0, 04/02, page 1018 of 1064
HD6417751VF133
*2
Symbol Min Max
t 3.5 —
DRQS
t 1.5 —
DRQH
— 8
DRAKD
t 5 —
NMIH
30 —
t 5 —
NMIL
30 —
t 50 —
TCKcyc
t 15 —
TCKH
t 15 —
TCKL
t — 10
TCKr
— 10
TCKf
t 10 —
ASEBRKS
10 —
ASEBRKH
t 15 —
TDIS
15 —
TDIH
t 0 12
TDO
t 2 —
PINBRK
= 1.5 V typ, Ta = –20 to 75
DD
= 1.8 V typ, Ta = –20 to 75
DD
= 1.8 V typ, Ta = –40 to 85
DD
HD6417751BP167
HD6417751BP167I
HD6417751F167
HD6417751F167I
*3
Min Max Unit
3.5 — ns
1.5 — ns
— 8 ns
5 — t
cyc
30 — ns
5 — t
cyc
30 — ns
50 — ns
15 — ns
15 — ns
— 10 ns
— 10 ns
10 — t
cyc
10 — t
cyc
15 — ns
15 — ns
0 10 ns
2 — Pcyc*


C, C = 30 pF, PLL2 on
L

C, C = 30 pF, PLL2 on
L


C, C = 30 pF, PLL2 on
L
Figure Notes
23.64
23.64
23.64
23.69 Normal
or sleep
mode
23.69 Standby
mode
23.69 Normal
or sleep
mode
23.69 Standby
mode
23.65,
23.67
23.65
23.65
23.65
23.65
23.66
23.66
23.67
23.67
23.67
1
23.68