Write-Back Buffer; Write-Through Buffer; Ram Mode; Figure 4.4 Configuration Of Write-Back Buffer - Hitachi SH7751 Hardware Manual

4.3.4

Write-Back Buffer

In order to give priority to data reads to the cache and improve performance, the SH7751 Series
has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a
dirty cache entry into external memory as the result of a cache miss. The write-back buffer
contains one cache line of data and the physical address of the purge destination.
Physical address bits [28:5]
4.3.5

Write-Through Buffer

The SH7751 Series has a 64-bit buffer for holding write data when writing data in write-through
mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as
soon as the write to the write-through buffer is completed, without waiting for completion of the
write to external memory.
4.3.6

RAM Mode

Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. The operand
cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511. In SH7751-
compatible-mode in the SH7751R, the 8 kbytes of operand cache entries 256 to 511 are used as
RAM. In cache-double-mode in the SH7751R, the total 16 kbytes of entries 256 to 511 in each
way of the operand cache are used as RAM. Other entries can still be used as cache. RAM can be
accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-
size data reads and writes can be performed in the operand cache RAM area. Instruction fetches
cannot be performed in this area.
Note that in the SH7751R, OC index mode cannot be used when RAM mode is used.
An example of RAM use is shown below. Here, the 4 kbytes comprising OC entries 128 to 256
are designated as RAM area 1, and the 4 kbytes comprising OC entries 384 to 511 as RAM area 2.


When OC index mode is off (CCR.OIX = 0)
H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1
H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1
LW0

Figure 4.4 Configuration of Write-Back Buffer

Physical address bits [28:0]

Figure 4.5 Configuration of Write-Through Buffer

LW1 LW2 LW3
LW0
LW4 LW5 LW6
LW1
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LW7