Synchronous Dram Interface - Hitachi SH7751 Hardware Manual

13.3.5

Synchronous DRAM Interface

Direct Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the

signal, it can be connected to external memory space areas 2 and 3 using
control signals in common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 3
is synchronous DRAM interface; if set to 011, areas 2 and 3 are both synchronous DRAM
interface.
The SH7751 Series supports burst read and burst write operations with a burst length of 4 as a
synchronous DRAM operating mode. The data bus width is 32 bit, and the SZ size bits in MCR
must be set to 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is
performed in a cache fill/copy-back cycle. In write-through area write operations and non-
cacheable area read/write operations, 16-byte data is read even in a single read because accessing
synchronous DRAM is by burst-length 4 burst read/write operations. 16-byte data transfer is also
performed in a single write, but DQMn is not asserted when unnecessary data is transferred.
In the SH7751R, an 8-burst-length burst read/burst write mode is also supported as a synchronous
DRAM operating mode. The data bus width is 32 bits, and the SZ size bits in MCR must be set to
11. Burst enable bit BE in MCR is ignored, and a 32-byte burst transfer is performed in a cache
fill/copy-back cycle. For write-through area writes and non-cacheable area reads/writes,
synchronous DRAM is accessed with an 8-burst-length burst read/write, and therefore 32 bytes of
data are read even in the case of a single read. In the case of a single write, 32-byte data transfer is
performed but DQMn is not asserted in the case of an unnecessary data transfer. For a description
of the case where an 8-burst-length setting is made, see section 13.3.6, Burst ROM Interface. For
information on the burst length, see section 13.2.10, Synchronous DRAM Mode Register
(SDMR), and section 13.3.5, Power-On Sequence.
The control signals for connection of synchronous DRAM are
DQM0 to DQM3, and CKE. All the signals other than
signals other than CKE are valid and latched only when
DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low)
when the frequency is changed, when the clock is unstable after the clock supply is stopped and
restarted, or when self-refreshing is performed, and is always asserted (high) at other times.
Commands for synchronous DRAM are specified by
signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks
(PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ),
read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register
setting (MRS).
Byte specification is performed by DQM0 to DQM3. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 32 bits, in big-endian mode
DQM3 specifies an access to address 4n, and DQM0 specifies an access to address 4n + 3. In

  
, , RD/
 
and are common to all areas, and
 
or is asserted. Synchronous

  

, , RD/ , and specific address
Rev. 3.0, 04/02, page 393 of 1064


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