Pci Configuration Register 1 (Pciconf1) - Hitachi SH7751 Hardware Manual

Bits 31 to 16—DEVID15 to 0: These bits specify the device ID of the SH7751 or SH7751R
allocated by the PCI device vendor. H'3505 (fixed in hardware) for the SH7751, and H'350E
(fixed in hardware) for the SH7751R.
Bits 15 to 0—DNVID15 to 0: These bits specify Hitachi as the PCI device maker (vendor ID).
(H'1054: fixed in hardware)
22.2.2

PCI Configuration Register 1 (PCICONF1)

Bit: 31
DPE
Initial value: 0
PCI-R/W: R/WC
PP Bus-R/W: R/WC
Bit: 23
FBBC
Initial value: 1
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 7
WCC
Initial value: 1
PCI-R/W: R/W
PP Bus-R/W: R/W
Note: Cleared by writing WC:1. (Writing of 0 is ignored.)
PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the
status and command PCI configuration registers stipulated in the PCI local bus specifications. The
status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to
0 (command register) contain the settings required for initiating transfers on the PCI bus.
Rev. 3.0, 04/02, page 812 of 1064
30 29
SSE RMA
0 0
R/WC R/WC
R/WC R/WC
22 21
UDF 66M
0 0
R R
R/W R/W
14 13
— —
0 0
R R
R R
6 5
PER VPS MWIE
0 0
R/W R
R/W R
28 27
RTA STA DEV1
0 0
R/WC R/WC
R/WC R/WC
20 19
PM —
1 0
R R
R R
12 11
— —
0 0
R R
R R
4 3
SPC
0 0
R R
R R
26 25
DEV0
0 1
R R R/WC
R R R/WC
18 17
— —
0 0
R R
R R
10 9
— PBBE
0 0
R R
R R
2 1
BUM MES
0 0
R/W R/W
R/W R/W
24
DPD
0
16
—
0
R
R
8
SER
0
R/W
R/W
0
IOS
0
R/W
R/W