On-Chip Peripheral Module Interrupts - Hitachi SH7751 Hardware Manual

19.2.3

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are generated by the following ten modules:


Hitachi user debug interface unit (H-UDI)


Direct memory access controller (DMAC)


Timer unit (TMU)


Realtime clock (RTC)


Serial communication interface (SCI)


Serial communication interface with FIFO (SCIF)


Bus state controller (BSC)


Watchdog timer (WDT)


I/O port (GPIO)


PCI bus controller (PCIC)
Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the
interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register
value as a branch offset in the exception handling routine.
A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A
to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00).
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by on-chip peripheral
module interrupt handling.
On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be
carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an
erroneous interrupt from an interrupt source that should have been updated, first read the on-chip
peripheral register containing the relevant flag, then clear the BL bit to 0. Furthermore, in case of
an interrupt of TMU channels 3 and 4 and PCIC, read the interrupt factor register 00
(INTREQ00). This will secure the necessary timing internally. When updating a number of flags,
there is no problem if only the register containing the last flag updated is read.
If flag updating is performed while the BL bit is cleared to 0, the program may jump to the
interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is
initiated due to the timing relationship between the flag update and interrupt request recognition
within the chip. Processing can be continued without any problem by executing an RTE
instruction.
Rev. 3.0, 04/02, page 735 of 1064