Interrupt Factor Register (Sdint); Boundary Scan Register (Sdbsr) - Hitachi SH7751 Hardware Manual

21.2.4

Interrupt Factor Register (SDINT)

The interrupt factor register (SDINT) is a 16-bit register that can be read/written from the CPU.
When a (H-UDI interrupt) command is set in the SDIR (Update-IR) via the H-UDI pin, the
INTREQ bit is set to 1. While SDIR has the "H-UDI interrupt" command, the SDINT register is
connected between H-UDI pins TDI and TDO, and can be read as a 32-bit register. The high 16
bits are 0 and the low 16 bits are SDINT.
Only 0 can be written to the INTREQ bit from the CPU. While this bit is 1, the interrupt request
continues to be generated, and must therefore be cleared to 0 by the interrupt handler. This register



is initialized by
Bit: 15
—
Initial value: 0
R/W: R
Bit: 7
—
Initial value: 0
R/W: R
Bits 15 to 1— Reserved: These bits always read as 0, and should only be written with 0.
Bit 0—Interrupt Request Bit (INTREQ): Shows the existence of an interrupt request from the
"H-UDI interrupt" command. The interrupt request can be cleared by writing 0 to this bit from the
CPU. When 1 is written to this bit, the existing value is retained.
21.2.5

Boundary Scan Register (SDBSR)

The boundary scan register (SDBSR) is a shift register on the PAD for controlling the chip's I/O
pins. Using the EXTEST and SAMPLE/PRELOAD commands, it can perform a JTAG (IEEE Std
1149.1)-compatible boundary scan test. Table 21.3 shows the relationship between SH7751 Series
pins and the boundary scan register.
or when in the Test Logic Reset state.
14 13
— —
0 0
R R
6 5
— —
0 0
R R
12 11
— —
0 0
R R
4 3
— —
0 0
R R
Rev. 3.0, 04/02, page 783 of 1064
10 9
— —
0 0
R R
2 1
— — INTREQ
0 0
R R R/W
8
—
0
R
0
0