Table 13.15 Example Of Correspondence Between Sh7751 Series And Synchronous Dram - Hitachi SH7751 Hardware Manual

Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM

Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0)
SH7751 Series Address Pin
RAS Cycle
A13 A21
A12 A20
A11 A19
A10 A18
A9 A17
A8 A16
A7 A15
A6 A14
A5 A13
A4 A12
A3 A11
A2 A10
A1 Not used
A0 Not used
Burst Read: The timing chart for a burst read is shown in figure 13.24. In the following example
it is assumed that two 512k
data width is used. The burst length is 4. After the Tr cycle in which the ACTV command is
output, a READ command is issued in the Tc1 cycle and, 4 cycles after that, a READA command
is issued and read data is fetched on the rising edge of the external command clock (CKIO) from
cycle Td1 to cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on
the READA command inside the synchronous DRAM; no new access command can be issued to
the same bank during this cycle. In the SH7751 Series, the number of Tpc cycles is determined by
the specification of bits TPC2–TPC0 in MCR, and commands are not issued for the synchronous
DRAM during this interval.
The example in figure 13.24 shows the basic cycle. To connect slower synchronous DRAM, the
cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by bits
RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case
of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous
DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ
command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles
independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2.
This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
CAS Cycle
A21 A11
H/L A10
0 A9
0 A8
A9 A7
A8 A6
A7 A5
A6 A4
A5 A3
A4 A2
A3 A1
A2 A0
Not used Not used
Not used Not used
 
16-bit 2-bank synchronous DRAMs are connected, and a 32-bit
Synchronous DRAM Address Pin
BANK select bank address
Address precharge setting
Address
Rev. 3.0, 04/02, page 395 of 1064
Function