Figure 13.19(1) Dram Burst Bus Cycle, Ras Down Mode Start (Fast Page Mode, Rcd = 0, Anw = 0) - Hitachi SH7751 Hardware Manual

Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
CKIO
Row c1 c2 c8
Address
RD/
D31–D0
d1 d2 d8
(read)
D31–D0
d1 d2 d8
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 385 of 1064