Configuration Of The Dmac (Sh7751R); Block Diagram Of The Dmac; Figure 14.53 Block Diagram Of The Dmac - Hitachi SH7751 Hardware Manual

14.6

Configuration of the DMAC (SH7751R)

14.6.1

Block Diagram of the DMAC

Figure 14.53 is a block diagram of the DMAC in the SH7751R.
On-chip
peripheral
module
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
,
/
D[31:0] External bus
ID[1:0]
DMAOR: DMAC operation register
SAR: DMAC source address register
DAR: DMAC destination address register
DMATCR: DMAC transfer count register
CHCR: DMAC channel control register
Rev. 3.0, 04/02, page 550 of 1064
32B data
buffer
Bus state
controller

Figure 14.53 Block Diagram of the DMAC

DMAC module
Count control
Registr control
Activation
control
Request
priority
control
Bus
interface
8
Request
dreq0–7
DTR command buffer
CH0
DBREQ
DDTMODE CH4
BAVL
DDTD
48 bits
id[2:0]
tdack
SAR0–7
DAR0–7
DMATCR0–7
CHCR0–7
DMAOR
queclr0–7
dmaqueclr0-7
SAR0, DAR0, DMATCR0,
CHCR0 only
DDT module
Request controller
CH1 CH2 CH3
CH5 CH6 CH7