Figure 22.21(2) Data Alignment At Target Memory Transfer (Little-Endian Local Bus) - Hitachi SH7751 Hardware Manual

Target memory read transfers (local bus → PCI bus) when local bus is little endian
Size
LW
Target memory write transfers (local bus ← PCI bus) when local bus is little endian
Size
B
B
B
B
W
W
B + B
B + B
B + B
B + B
W + B
W + B
B + W
B + W
—
LW

Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus)

Rev. 3.0, 04/02, page 916 of 1064
Local bus
31 0
B3 B2 B1 B0
Local bus
31 0
B0
B1
B2
B3
B1 B0
B3 B2
B0 +
B1 + B3
B0 + B3
B1 +
B1 B0 +
B1 B0 + B3
B0 + B3 B2
B1 + B3 B2
—
B3 B2 B1 B0
31
B3 B2 B1 B0
31
B3
B3 B2
B2
B3
B3
B2
B2
B3
B3 B2
B3 B2 B1
B3 B2 B1 B0
PCI bus
BE
0
H'0 to H'F
PCI bus
BE
0
1110
B0
1101
B1
1011
B2
0111
B1 B0 1100
0011
1010
B2 B0
0101
B1
0110
B0
1001
B2 B1
B2 B1 B0 1000
B1 B0 0100
0010
B0
0001
1111
0000