Figure 13.70 Byte Control Sram Basic Read Cycle (One Internal Wait Cycle) - Hitachi SH7751 Hardware Manual

T1 Tw T2
CKIO
A25–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)

Rev. 3.0, 04/02, page 453 of 1064