Figure 13.41 Burst Rom Basic Access Timing - Hitachi SH7751 Hardware Manual

T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.41 Burst ROM Basic Access Timing

Rev. 3.0, 04/02, page 420 of 1064