Pci Interrupt Register (Pciint) - Hitachi SH7751 Hardware Manual

22.2.20 PCI Interrupt Register (PCIINT)

Bit: 31
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
M_LOCK
ON
Initial value: 0
PCI-R/W: R/WC
PP Bus-R/W: R/WC
Bit: 7
ADRPER
R
Initial value: 0
PCI-R/W: R/WC
PP Bus-R/W: R/WC
Note: WC: Cleared by writing "1". (Writing of 0 is ignored.)
The PCI interrupt register (PCIINT) is a 32-bit register that saves the error source when an error
occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus, or
when the PCIC is the PCI master or PCI target. This register can be read from both the PP bus and
PCI bus. Also, 1 can be written from either the PP bus or PCI bus to perform a write-clear in
which the detection bit is cleared to its initial value (0).
The PCIINT register is initialized to H'00000000 at a power-on reset or software reset.
When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt
detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear)
Rev. 3.0, 04/02, page 846 of 1064
30 29
— —
0 0
R R
R R
22 21
— —
0 0
R R
R R
14 13
T_TGT_A —
BORT
0 0
R/WC R
R/WC R
6 5
SERR_D T_DPER
ET R_WT
0 0
R/WC R/WC
R/WC R/WC
28 27
— —
0 0
R R
R R
20 19
— —
0 0
R R
R R
12 11
— —
0 0
R R
R R
4 3
T_PERR_ M_TGT_A M_MST_
DET BORT
0 0
R/WC R/WC
R/WC R/WC
26 25
— —
0 0
R R
R R
18 17
— —
0 0
R R
R R
10 9
— TGT_RET MST_DIS
RY
0 0
R R/WC
R R/WC
2 1
M_DPER M_DPER
ABORT R_WT
0 0
R/WC R/WC
R/WC R/WC
24
—
0
R
R
16
—
0
R
R
8
0
R/WC
R/WC
0
R_RD
0
R/WC
R/WC