Hitachi SH7751 Hardware Manual page 163

Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Interrupt Completion
type
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3–IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
*2 The priority order of external interrupts and peripheral module interrupts can be set by
software.
*3 SH7751R only
Rev. 3.0, 04/02, page 124 of 1064
Exception
Peripheral H-UDI H-UDI
module
GPIO GPIOI
interrupt
DMAC DMTE0
(module/
source)
DMTE1
DMTE2
DMTE3
DMTE4*
DMTE5*
DMTE6*
DMTE7*
DMAE
SCIF ERI
RXI
BRI
TXI
PCIC(0) PCISERR
PCIC(1) PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
Priority Priority
Level Order
4 *2
3
3
3
3
Vector
Address Offset
(VBR) H'600
Exception
Code
H'600
H'620
H'640
H'660
H'680
H'6A0
H'780
H'7A0
H'7C0
H'7E0
H'6C0
H'700
H'720
H'740
H'760
H'A00
H'AE0
H'AC0
H'AA0
H'A80
H'A60
H'A40
H'A20