Hitachi SH7751 Hardware Manual page 379

Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait
states to be inserted for area 0. For the case where an MPX interface setting is made, see table
13.7.
Bit 5: A0W2 Bit 4: A0W1
0 0
1
1 0
1
Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Bit 2: A0B2 Bit 1: A0B1
0 0
1
1 0
1
Rev. 3.0, 04/02, page 340 of 1064
Bit 3: A0W0 Inserted Wait States
0 0
1 1
0 2
1 3
0 6
1 9
0 12
1 15 (Initial value)
Wait States Inserted from
Bit 0: A0B0 Second Data Access Onward
0 0
1 1
0 2
1 3
0 4
1 5
0 6
1 7 (Initial value)
Description
First Cycle
Description
Burst Cycle (Excluding First Cycle)
 
Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
 
Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled